In transfer gate logic (also called transmission gates) a combination of P-type and N-type MOSFETS are used because of the inherent difficulty of each to provide an unaltered copy of high and low input levels at the output, which is a requirement in transfer logic. For instance, the voltage across a PMOS transistor can only be brought as low as 1 threshold voltage, Vt, above zero. Therefore, passing a logic zero could not be obtained. This is because once the source-to-gate voltage (Vg = 0 for PMOS) drops below the threshold voltage, the transistor will enter the cut-off mode of operation. A similar argument can be made for the NMOS device. It is impossible for the NMOS to transmit a signal above Vdd-Vgs (which is one threshold voltage below the voltage level Vdd). Therefore the combination of both transistors is used to implement the transmission gate which has been a source for rapid advance in VLSI development.
